Title |
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance |
|---|---|
Involved |
Valeriy Sukharev (Verfasser)
Armen Kteyan (Verfasser) Jun-Ho Choy (Verfasser) Henrik Hovsepyan (Verfasser)
Ara Markosian (Verfasser)
Ehrenfried Zschech (Verfasser) Rene Huebner (Verfasser) SpringerLink (Online service) (Sonstige) |
Published in |
Journal of electronic testing : theory and applications 28, 1, 5.11.2011, date:2.2012, Seite 63-72 |
Published |
2011 |
Language |
|
Country |
|
Topic |
|
Subject |
Computer-Aided Engineering (CAD, CAE) and Design. |
Persistent identifier |
urn:nbn:de:101:1-2019062623053153892002 (URN) |
Record ID |
1189301342 |
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