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Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj et al.

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

Erlangen: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2021

Title

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems / Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey

Involved 

Marc Reichenbach (Verfasser)
Johannes Knödtel (Verfasser)
Sebastian Rachuj (Verfasser)
Dietmar Fey (Verfasser)

Published

Erlangen: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU)
2021

Extent

Online-Ressource

Language

Englisch

Country

Deutschland

Topic

Informatik

Subject

Arithmetic and logic units
processor architectures
RISC
ternary arithmetic

DDC notation

004.16

Persistent identifier

urn:nbn:de:bvb:29-opus4-193226 (URN)
10.1109/ACCESS.2021.3063238 (DOI)

Further information

In: IEEE Access 9 (2021): S. 43684-43700. <https://ieeexplore.ieee.org/document/9366755>

Record ID

1257972731
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