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Tomohiro Yoneda, Bernd-Holger Schlingloff and SpringerLink (Online service)

Efficient Verification of Parallel Real–Time Systems

Published in: Formal methods in system design : an international journal 11, 2, date:8.1997

Title

Efficient Verification of Parallel Real–Time Systems

Involved 

Tomohiro Yoneda (Verfasser)
Bernd-Holger Schlingloff (Verfasser)
SpringerLink (Online service) (Sonstige)

Published in

Formal methods in system design : an international journal 11, 2, date:8.1997, Seite 187-215

Published

1997

Language

Englisch

Country

Deutschland

Topic

Informatik

Subject

Electronic Circuits and Systems.
Electrical and Electronic Engineering.
Computer-Aided Engineering (CAD, CAE) and Design.
Software Engineering.

Persistent identifier

urn:nbn:de:101:1-2023092721510350883279 (URN)
10.1023/A:1008682131325 (DOI)

Record ID

1304200329
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