Title |
Test pattern generation and verification for logic circuits : an implication graph based approach / Paul Tafertshofer |
|---|---|
Involved |
Paul Tafertshofer (Verfasser) |
Published |
München: Hieronymus |
Edition |
Als Typoskr. gedr. |
Extent |
III, 190, XXVI S. |
Thesis |
Zugl.: München, Techn. Univ., Diss. |
ISBN |
978-3-89791-192-5 |
Language |
|
Topic |
|
Subject |
Digitale integrierte Schaltung, Testmustergenerierung, Selbsttest, Fehlererkennung |
Series |
Informationstechnik |
Record ID |
962761265 |
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